Title
Optimization of gate-on-source-only tunnel FETs with counter-doped pockets Optimization of gate-on-source-only tunnel FETs with counter-doped pockets
Author
Faculty/Department
Faculty of Sciences. Physics
Publication type
article
Publication
New York, N.Y. ,
Subject
Physics
Source (journal)
IEEE transactions on electron devices. - New York, N.Y.
Volume/pages
59(2012) :8 , p. 2070-2077
ISSN
0018-9383
ISI
000306920200011
Carrier
E
Target language
English (eng)
Full text (Publishers DOI)
Affiliation
University of Antwerp
Abstract
We investigate a promising tunnel FET configuration having a gate on the source only, which is simultaneously exhibiting a steeper subthreshold slope and a higher ON-current than the lateral tunneling configuration with a gate on the channel. Our analysis is performed based on a recently developed 2-D quantum-mechanical simulator calculating band-to-band tunneling and including quantum confinement (QC). It is shown that the two disadvantages of the structure, namely, the sensitivity to gate alignment and the physical oxide thickness, are mitigated by placing a counter-doped parallel pocket underneath the gate-source overlap. The pocket also significantly reduces the field-induced QC. The findings are illustrated with all-Si and all-Ge gate-on-source-only tunnel field-effect transistor simulations.
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