Publication
Title
Optimization of gate-on-source-only tunnel FETs with counter-doped pockets
Author
Abstract
We investigate a promising tunnel FET configuration having a gate on the source only, which is simultaneously exhibiting a steeper subthreshold slope and a higher ON-current than the lateral tunneling configuration with a gate on the channel. Our analysis is performed based on a recently developed 2-D quantum-mechanical simulator calculating band-to-band tunneling and including quantum confinement (QC). It is shown that the two disadvantages of the structure, namely, the sensitivity to gate alignment and the physical oxide thickness, are mitigated by placing a counter-doped parallel pocket underneath the gate-source overlap. The pocket also significantly reduces the field-induced QC. The findings are illustrated with all-Si and all-Ge gate-on-source-only tunnel field-effect transistor simulations.
Language
English
Source (journal)
IEEE transactions on electron devices. - New York, N.Y.
Publication
New York, N.Y. : 2012
ISSN
0018-9383
Volume/pages
59:8(2012), p. 2070-2077
ISI
000306920200011
Full text (Publisher's DOI)
UAntwerpen
Faculty/Department
Research group
Publication type
Subject
Affiliation
Publications with a UAntwerp address
External links
Web of Science
Record
Identification
Creation 13.09.2012
Last edited 08.07.2017
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