|
Title
|
|
|
|
Statistically aware SRAM memory array design
| |
|
Author
|
|
|
|
| |
|
Abstract
|
|
|
|
| Increasing process-parameter variations due to technology scaling to nanometer nodes have a significant impact on the circuit design flow. As shown repeatedly in previous work, a worst-case design approach is no longer feasible to guarantee a yielding design. Furthermore, the study of these process-parameter variations on the distributions of performance parameters has been done extensively in the past. However this will not improve the circuit design unless the statistical it formation is considered during the optimization of the design. In this paper, we propose a method to minimize the leakage power of a SRAM cell while satisfying conflicting functionality and delay constraints, under these technology variations. Additionally, this method generates power-stability trade-offs to optimize the circuit for a given yield at design time. Even at cell level, statistically aware design allows both minimal stand by leakage power and minimal area. |
| |
|
Language
|
|
|
|
English
| |
|
Source (journal)
|
|
|
|
ISQED 2006: Proceedings of the 7th International Symposium on Quality Electronic Design
| |
|
Source (book)
|
|
|
|
7th International Symposium on Quality Electronic Design, MAR 27-29, 2006, San Jose, CA
| |
|
Publication
|
|
|
|
2006
| |
|
ISBN
|
|
|
|
0-7695-2523-7
| |
|
Volume/pages
|
|
|
|
(2006)
, p. 25-30
| |
|
ISI
|
|
|
|
000237231000008
| |
|