On the combined impact of soft and medium gate oxide breakdown and process variability on the parametric figures of SRAM components
Los alamitos :Ieee computer soc
MTDT'06: 2006 IEEE International Workshop on Memory Technology, Design,
and Testing, Proceedings
14th IEEE International Workshop on Memory Technology, Design and, Testing, AUG 02-04, 2006, Taipei, TAIWAN
, p. 71-76
University of Antwerp
The effect of gate oxide breakdown has long been studied in the context of device functional failure in the past. As technology node scales down to Very Deep SubMicron (VDSM) era, such an effect starts to influence the performance and power consumption of digital circuits within their lifetime. Meanwhile, process variability like threshold voltage shift due to e.g., device dopant fluctuation and/or line edge roughness effects also leads to significant shift of the parametric figures for performance and energy of these circuits at sub 100nm era. Further scaling will definitely lead to the co-existence of both effects in a single circuit. In this paper, we present the experimental analysis on the impact combining gate oxide breakdown and process variability on the energy and delay figures of SRAM cell and Sense Amplifier Hspice simulations at 65nm technology node indicate a significantly larger shift in both energy and delay of these components than in the cases with either single effect when using the thinner oxide found in 45132 nm technologies. The actual behavior of the circuits under such a situation becomes more difficult to predict and control, thus bringing a huge challenge to a successful design in the VDSM era.