Exploration of system-level trade-offs for application mapping in multiprocessor system-on-chips
2005 PhD Research in Microelectronics and Electronics, Vols 1 and 2, Proceedings
International Conference on PhD Research in Microelectronics and, Electronics (PRIME 2005), Lausanne, SWITZERLAND
, p. 426-429
University of Antwerp
In order to meet heavy constraints for power, performance and flexibility, applications on future hand-held devices will be executed on architectures with multiple processors. However, this will only succeed if the application is mapped using an efficient, coarse-grained parallelization. The final performance of the parallel-executed applications heavily depends on the partitioning, the architecture characteristics, the memory hierarchy,... Since it is very hard for a designer to oversee the effect of these interactions manually, tools should be developed. The current PhD explores these issues based on real-life examples of wavelet still image, video and volumetric coding.