| Title |
|
|
|
Ge deep sub-micron pFETs with etched TaN metal gate on a High-K dielectric, fabricated in a 200mm silicon prototyping line
| |
| Author |
|
|
|
| |
| Abstract |
|
|
|
| We report for the first time on deep sub-micron Ge pFETs with physical gate lengths down to 0.15 mum. The devices are made using a silicon-like process flow, with a directly etched gate stack consisting of TaN gate on an ALD or MOCVD HfO(2) dielectric. Promising drive currents are found. Various issues such as the severe short channel effects (SCE), the increased diode leakage compared to Si and the high amount of interface states (N(it)) are addressed. The need for an alternative Ge substrate pre-treatment and subsequent High-K gate dielectric deposition to push EOT values below 1nm is illustrated. | | |
| Language |
|
|
|
English
| |
| Source (journal) |
|
|
|
ESSDERC 2004: PROCEEDINGS OF THE 34TH EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE | |
| Source (book) |
|
|
|
34th European Solid-State Device Research Conference (ESSDERC 2004), SEP 21-23, 2004, Leuven, BELGIUM | |
| Publication |
|
|
|
New york : Ieee, 2004
| |
| ISBN |
|
|
|
0-7803-8478-4
| |
| Volume/pages |
|
|
|
(2004), p. 189-192
| |
| ISI |
|
|
|
000225486100040
| |
| Full text (Publisher's DOI) |
|
|
| | |
|