Title
Extending on-die wiring hierarchy with wafer level packaging concepts
Author
Publication type
conferenceObject
Publication
Subject
Computer. Automation
Source (journal)
Proceedings of the IEEE 2004 Internatonal Interconnect technology conference
Source (book)
7th Annual International Interconnect Technology Conference, JUN 07-09, 2004, Burlingame, CA
Volume/pages
(2004) , p. 105-107
ISBN
0-7803-8308-7
ISI
000223636300031
Carrier
E
Target language
English (eng)
Full text (Publishers DOI)
Affiliation
University of Antwerp
Abstract
Wafer Level Package (WLP) redistribution layer interconnects can be effectively used for countering on-die global wiring challenges. To demonstrate this, we fabricated WLP test chips with two configurations namely IMPS and Microstrip transmission lines in WLP layers. Experimental results indicate superior electrical performance. Near speed of light propagation is observed with insignificant signal distortion. We compare the WLP layers interconnect performance with a representative 70nm node upsized global interconnect. Details on the WLP technology are also provided.
E-info
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