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Title
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Extending on-die wiring hierarchy with wafer level packaging concepts
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Author
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Abstract
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| Wafer Level Package (WLP) redistribution layer interconnects can be effectively used for countering on-die global wiring challenges. To demonstrate this, we fabricated WLP test chips with two configurations namely IMPS and Microstrip transmission lines in WLP layers. Experimental results indicate superior electrical performance. Near speed of light propagation is observed with insignificant signal distortion. We compare the WLP layers interconnect performance with a representative 70nm node upsized global interconnect. Details on the WLP technology are also provided. |
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Language
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English
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Source (journal)
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Proceedings of the IEEE 2004 Internatonal Interconnect technology conference
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Source (book)
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7th Annual International Interconnect Technology Conference, JUN 07-09, 2004, Burlingame, CA
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Publication
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2004
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ISBN
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0-7803-8308-7
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DOI
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10.1109/IITC.2004.1345705
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Volume/pages
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(2004)
, p. 105-107
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ISI
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000223636300031
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Full text (Publisher's DOI)
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