Title
Digital ground bounce reduction by phase modulation of the clock Digital ground bounce reduction by phase modulation of the clock
Author
Publication type
conferenceObject
Publication
Subject
Computer. Automation
Source (journal)
Design, automation and test in Europe conference and exhibition, vols 1 and 2, proceedings
Source (book)
Design, Automation and Test in Europe Conference and Exhibition (DATE, 04), FEB 16-20, 2004, Paris, FRANCE
Volume/pages
(2004) , p. 88-93
ISBN
0-7695-2085-5
ISI
000189434000015
Carrier
E
Target language
English (eng)
Full text (Publishers DOI)
Affiliation
University of Antwerp
Abstract
The digital switching noise that propagates through the chip substrate to the analog circuitry on the same chip is a major limitation for mixed-signal SoC integration. In synchronous digital systems, digital circuits switch simultaneously on the clock edge, hereby generating a large ground bounce. In order to reduce the spectral peaks in the ground bounce spectrum, we combine the two techniques: (1) phase modulation of the clock and (2) introducing intended clock skews to spread the switching activities. Experimental results show around 16 dB reduction in the spectral peaks of the noise spectrum when these two techniques are combined. These two techniques are believed to be good candidates for the development of methodologies for digital low-noise design techniques in future CMOS technologies.
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