Title
Highly scalable network on chip for reconfigurable systemsHighly scalable network on chip for reconfigurable systems
Author
Publication type
conferenceObject
Publication
Subject
Computer. Automation
Source (journal)
International symposium on system-on-chip, proceedings
Source (book)
5th Annual International Symposium on System-on-Chip, NOV 19-21, 2003, Tampere, FINLAND
Volume/pages
(2003), p. 79-82
ISBN
0-7803-8160-2
ISI
000189409300022
Carrier
E
Target language
English (eng)
Full text (Publishers DOI)
Affiliation
University of Antwerp
Abstract
An efficient methodology for building the billion-transistors systems on chip of tomorrow is a necessity. Networks on chip promise to be the solution for the numerous technological, economical and productivity problems. We believe that different types of networks will be required for each application domains. Our approach therefore is to have a very flexible network design, highly scalable, that allows to easily accommodate the various needs. This paper presents the design of our network on chip, which is part of the platform we are developing for reconfigurable systems. The present design allows us to instantiate arbitrary network topologies, has a low latency and a high throughput.
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