Publication
Title
Highly scalable network on chip for reconfigurable systems
Author
Abstract
An efficient methodology for building the billion-transistors systems on chip of tomorrow is a necessity. Networks on chip promise to be the solution for the numerous technological, economical and productivity problems. We believe that different types of networks will be required for each application domains. Our approach therefore is to have a very flexible network design, highly scalable, that allows to easily accommodate the various needs. This paper presents the design of our network on chip, which is part of the platform we are developing for reconfigurable systems. The present design allows us to instantiate arbitrary network topologies, has a low latency and a high throughput.
Language
English
Source (journal)
International symposium on system-on-chip, proceedings
Source (book)
5th Annual International Symposium on System-on-Chip, NOV 19-21, 2003, Tampere, FINLAND
Publication
2003
ISBN
0-7803-8160-2
Volume/pages
(2003), p. 79-82
ISI
000189409300022
Full text (Publisher's DOI)
UAntwerpen
Publication type
Subject
Affiliation
Publications with a UAntwerp address
External links
Web of Science
Record
Identification
Creation 03.01.2013
Last edited 09.09.2017
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