Publication
Title
Hierarchical run-time reconfiguration managed by an operating system for reconfigurable systems
Author
Abstract
The need for flexible computational power has motivated many researchers to incorporate run-time reconfigurable logic into their architectures. Most contemporary experiments include commercial FPGA's serving as reconfigurable hardware. Unfortunately, the FPGA does not exhibit the same run-time flexibility as the Instruction Set Processor (ISP) e.g. when it comes to ease and speed of setting tip a task. In addition, FPGA's tend to be less suited than traditional ISP's to accommodate control-flow dominated tasks. Obviously, it is possible to alleviate some of these issues by using a reconfiguration hierarchy (e.g. placing and configuring an ASIP or coarse grain reconfigurable block into the FPGA). This paper illustrates how our operating system transparently manages the complexin, of hierarchical reconfiguration. In addition, this paper highlights the benefits and drawbacks of employing multiple hierarchical levels of configuration. As a proof of concept, we developed a filtering application on top of an in-house 16 bit micro-controller and a parameterizable filter block, both instantiated inside an FPGA.
Language
English
Source (journal)
ERSA'03: PROCEEDINGS OF THE INTERNATIONAL CONFERENCE ON ENGINEERING OF
RECONFIGURABLE SYSTEMS AND ALGORITHMS
Source (book)
International Conference on Engineering of Reconfigurable Systems and, Algorithms, JUN 23-26, 2003, LAS VEGAS, NV
Publication
Athens : C s r e a press, 2003
ISBN
1-932415-05-X
Volume/pages
(2003), p. 81-87
ISI
000186578000011
UAntwerpen
Publication type
Subject
Affiliation
Publications with a UAntwerp address
External links
Web of Science
Record
Identification
Creation 03.01.2013
Last edited 16.08.2017
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