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Title
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Wafer-level electrical evaluation of vertical carbon nanotube bundles as a function of growth temperature
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Author
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Abstract
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| We have evaluated the resistance of carbon nanotubes (CNTs) grown at a CMOS-compatible temperature using a realistic integration scheme. The structural analysis of the CNTs by transmission electron microscopy (TEM) showed that the degree of graphitization decreased significantly when the growth temperature was decreased from 540 to 400 °C. The CNTs were integrated to form 150-nm-diameter vertical interconnects between a TiN layer and Cu metal trenches on 200 mm full wafers. Wafers with CNTs grown at low temperature were found to have a lower single-contact resistance than those produced at high temperatures. Thickness measurements showed that the low contact resistance is a result of small contact height. This height dependence is masking the impact of CNT graphitization quality on resistance. When benchmarking our results with data from the literature, a relationship between resistivity and growth temperature cannot be found for CNT-based vertical interconnects. |
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Language
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English
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Source (journal)
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Japanese journal of applied physics / Japan Society of Applied Physics. - Kyoto, 1962, currens
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Publication
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Kyoto
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2013
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ISSN
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0021-4922
1347-4065
[e-ISSN]
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DOI
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10.7567/JJAP.52.04CN02
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Volume/pages
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52
:42
(2013)
, p. 1-5
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Article Reference
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04CN02
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ISI
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000320002400150
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Medium
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E-only publicatie
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Full text (Publisher's DOI)
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Full text (publisher's version - intranet only)
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