Title
3D processing on 6 in. high resistive SOI wafers: fabrication of edgeless strip and pixel detectors 3D processing on 6 in. high resistive SOI wafers: fabrication of edgeless strip and pixel detectors
Author
Faculty/Department
Faculty of Sciences. Physics
Publication type
article
Publication
Subject
Physics
Source (journal)
Nuclear instruments and methods in physics research: A: accelerators, spectrometers, detectors and associated equipment
Volume/pages
607(2009) :1 , p. 85-88
ISSN
0168-9002
Carrier
E
Target language
English (eng)
Full text (Publishers DOI)
Affiliation
University of Antwerp
Abstract
An insight is given into the state-of-the-art 3D processing on 6 in. (150 mm) high resistivity silicon-on-insulator (SOI) wafers. The edgeless detector design offers some attractive properties for high-energy physics experiments and medical imaging studies, such as seamless tileability of the detectors with an inactive region width of about 10 μm. These detectors can be made very thin and the active edge avoids inhomogeneous electric fields and surface leakage currents. The paper summarizes the fabrication of edgeless detectors and the issues faced in the 3D processing on 6 in. SOI wafers. The fabrication process employed highly doped polysilicon filling in order to implement the active edges of the detector. Several planarization and ICP-etching steps were required. The layout had microstrip detectors with a pitch of 50 μm and sizes of 5×5 cm2 and 1×1 cm2, and Medipix2 compatible 1.4×1.4 cm2 pixel detectors. Also several test structures were fabricated. Electrical characterization of a 150-μm-thick edgeless diode showed low leakage currents, below 1 nA/cm2 at full depletion. The single-strip measurements showed leakage currents of about 10 pA/cm, regardless of the detector size. Low breakdown voltage of about 20 V was observed for several detectors. This might be caused by cracking of the detector edges following self-dicing. A simplified process flow for the fabrication of edgeless detectors is presented. The process is straightforward and fast because it excludes multiple ion coupled plasma (ICP)-etching steps, slow and wafer-damaging polysilicon filling and planarization steps. First images of the prototype are presented.
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